Project Documentation

Project: 		phytec

Controller: 		C167CR-L
Compiler: 		Keil C166 V3.00
Memory Model: 	SMALL

Codegenerator: 	DAvE 1-0-0

Date: 			25.02.98 10:26:47

Original startup file:
			Start167.a66

Modified startup file:
			Start.asm

Generated Files:
			MAIN.C
			MAIN.H

Main

Macros:
Functions:

	Function:
		void Project_Init(void)
	Description:
		This function initializes the microcontroller.
	Returnvalue:
		none
	Parameters:
		none

	Function:
		void main(void)
	Description:
		This is the main function.
	Returnvalue:
		none
	Parameters:
		none

Initialization:

	--- initialization of the SYSCON Register ---
	the following initialization is made in the Start.asm
	- the internal ROM area is mapped to segment 0
	- the segmentation is enabled (CSP is saved/restored during interrupt entry/exit)
	- the internal ROM is disabled: accesses to the ROM area use the external bus
	- the pin #BHE (byte high enable) is enabled
	- the system clock output is disabled
	- the pin #WR acts as #WRL and pin #BHE acts as #WRH
	- the on-chip X-Peripherals are enabled and can be accessed
	- accesses to the XBUS peripherals are done internally
	- external accesses to the XBUS peripherals are disabled

	--- initialization of the BUSCON 0-4 and ADRRSEL Registers 1-4 ---
	for the Keil Compiler the initialization is made in the Start.asm

	---------- external bus 0 is enabled ----------
	- 16-bit demultiplexed bus
	- memory cycle time control: 0 waitstates
	- read/write delay control: activate signal 1 TCL after falling edge of ALE
	- signal configuration: disable READY signal
	- chip select mode: address chip select
	- memory tristate control: no waitstate
	- ALE lengthening control: normal ALE signal

	---------- external bus 1 is enabled ----------
	- 16-bit demultiplexed bus
	- memory cycle time control: 0 waitstates
	- read/write delay control: activate signal 1 TCL after falling edge of ALE
	- signal configuration: disable READY signal
	- chip select mode: address chip select
	- memory tristate control: no waitstate
	- ALE lengthening control: normal ALE signal